CS641 Syllabus, Spring 2011

Computer Architecture

Official Description: An examination of the designs for hierarchical memory systems including caches and virtual memory systems, pipeline design techniques, characteristics of RISC/CISC machines, multi-computer systems including multiprocessors and loosely-coupled computer systems, the micro engine and microprogrammed machines, vector and array processors, and the cost/performance trade-offs in all of the above designs

Professor: Betty O’Neil  (eoneil at cs.umb.edu)
Class meets MW 5:30-6:45 in M-1-616

Prerequistes:  CS310 and its prerequisite, CS240, i.e. Java programming and C programming, data structures.

Textbook: Computer Organization and Design: The Hardware/Software Interface, Fourth Edition by David A. Patterson, John L. Hennessy

Topics
This is tentative, and mainly derived from the schedule for CS61C at UC Berkeley At this site there are audio lectures available for older versions of this course, as well as slides and other resources.

Unit
 Lecture Topic Reading
1
 Introduction: Trends
 P&H (4th): 1.1-1.3 (available free online)
2
 Introduction to MIPS Assembly Language
 		P&H (4th): 2.1-2.3, 2.6, 2.7, 2.9, B.9,  B.10
MIPS: procedures
 P&H (4th): 2.8, 2.14
3
 HW/SW Interface: C to MIPS  P&H (4th): 2.10, 2.12 (pp. 139-142), 2.13
HW/SW Interface: Functions and Numbers
 		P&H (4th): 3.5 (pp. 242-250, 259-266), 3.8
4
 HW/SW Interface: Everything is a Number P&H (4th): 2.4, 2.5, 2.6, 3.5 (pp. 242-250)
HW/SW Interface: Compilation vs. Interpretation P&H (4th): 2.12, B.1-B.4
5
 Computer Components P&H (4th): 1.1-1.3
6
 Memory Hierarchy:Direct Mapped Cache P&H (4th): 5.1
Memory Hierarchy:Cache-Memory Interface&Perf P&H (4th): 5.2 (pp. 457-470), 5.3 (pp. 474-479)
7
 Data Level Parallelism: Flynn Taxonomy P&H (4th): 1.5, 1.6, 7.1, 7.2
Data Level Parallelism:  SSE SIMD Instructions P&H (4th): 7.4, 7.7, A.2 (pp. A-7-A-9)
8

 Thread Level Parallelism P&H (4th): 7.3, 5.8, 2.11
9

 Digital Logic
Transistors/Gates/Flip-flops 		P&H (4th): C.2-C.3 (on CD); Logic Handout, State Handout
10

 Single Cycle CPU Datapath and Control P&H (4th): 4.1, 4.3, 4.4
11
 Instruction Level Parallelism P&H (4th): 4.5, 4.6
Instruction Level Parallelism P&H (4th): 4.7, 4.8
12
 In More Depth:
Set-Associative Caches
 P&H (4th): Rest of 5.2, 5.3
In More Depth:
Multi-Level Caches 		P&H (4th): 5.8
13
 In More Depth:
Exceptions/Traps/Interrupts 		P&H (4th): 4.9
In More Depth:
Protection/Virtual Memory 		P&H (4th): 5.3-5.5, 5.10-5.12, 6.2, C.8
14
 Modern Microprocessors

Grading: simple point system

Midterm: 100 points, Final: 150 points, Assignments: various, about 150 points total

ACCOMMODATIONS:
Section 504 of the Americans with Disabilities Act of 1990 offers guidelines for curriculum modifications and adaptations for students with documented disabilities. If applicable, students may obtain adaptation recommendations from the Ross Center for Disability Services, M-1-401, (617-287-7430). The student must present these recommendations and discuss them with each professor within a reasonable period, preferably by the end of Drop/Add period.

STUDENT CONDUCT:
Students are required to adhere to the University Policy on Academic Standards and Cheating, to the University Statement on Plagiarism and the Documentation of Written Work, and to the Code of Student Conduct as delineated in the catalog of Undergraduate Programs, pp. 44-45, and 48-52. The Code is available online at: http://www.umb.edu/student_services/student_rights/code_conduct.html.