CS641 Intro to Verilog: see download link on webpage. It’s also on sf06 now, commands iverilog and vvp, same as on PC.

See list of docs for Verilog at end of this doc.

 Now Look at Verilog examples

Example: NAND gate, from Strozek tutorial

mynand.v:

// NAND gate simulator

module mynand(in0, in1, out);

  input in0, in1;

  output out;

  assign out = ~(in0 & in1);  // fixed from handed out copies

endmodule

can compile it: iverilog mynand.v

but can’t run it yet, need a “main”-like test bed code (this is explained in the Wawrzynek tutorial)

So here’s a testbed code, modified from W’s testbed for a MUX.

mynand_tb.v

// testbed for mynand

module testnand;

   reg a, b;

   wire f;

   reg expected;

   // instantiate a NAND gate using mynand:

   mynand nand1( .in0(a), .in1(b), .out(f));  //W’s preferred form

   // do a series of tests, at times 0, 10, 20, 30:

   initial

    begin

       #0   a=0; b=0; expected = 1;

       #10  a=1; b=0; expected = 1;

       #10  a=0; b=1; expected = 1;

       #10  a=1; b=1; expected = 0;

       #10 $stop;

    end

   // also, set up a signal-watching service so we can see what happens

   initial

     $monitor( "in0=%b in1=%b out=%b, expected out = %b time=%3d",

                  a, b, f, expected, $time);

endmodule

Compilation (can use –o mynand here, like C):

sf06.cs.umb.edu$ iverilog mynand.v mynand_tb.v

Execution:

sf06.cs.umb.edu$ vvp a.out

in0=0 in1=0 out=1, expected out = 1 time=  0

in0=1 in1=0 out=1, expected out = 1 time= 10

in0=0 in1=1 out=1, expected out = 1 time= 20

in0=1 in1=1 out=0, expected out = 0 time= 30

** VVP Stop(0) **

** Current simulation time is 40 ticks.

> finish

** Continue **

sf06.cs.umb.edu$

 

Can run 2 NANDs in parallel:

sf06.cs.umb.edu$ more mynand2_tb.v

module test2nand;

   reg a, b;

   wire f, f1;

   reg expected, exp2;

 

   mynand nand1( .in0(a), .in1(b), .out(f));

   mynand nand2( .in0(a), .in1(b), .out(f1));  <---second NAND, with own output wire

   initial

    begin

       #0   a=0; b=0; expected = 1;

       #10  a=1; b=0; expected = 1;

       #10  a=0; b=1; expected = 1;

       #10  a=1; b=1; expected = 0;

       #10 $stop;

    end

   initial

     $monitor( "in0=%b in1=%b out=%b, out1=%b, expected out = %b time=%3d",

                  a, b, f, f1, expected, $time);

endmodule

 

or equivalently: two mynand instantiation: two of same type, so we only have to mention the type once, as in C “int x,y;”:

 

   mynand nand1( .in0(a), .in1(b), .out(f)),

       nand2( .in0(a), .in1(b), .out(f1));  <---second NAND, with own output wire

 

 

sf06.cs.umb.edu$ vvp a.out

in0=0 in1=0 out=1, out1=1, expected out = 1 time=  0

in0=1 in1=0 out=1, out1=1, expected out = 1 time= 10

in0=0 in1=1 out=1, out1=1, expected out = 1 time= 20

in0=1 in1=1 out=0, out1=0, expected out = 0 time= 30

** VVP Stop(0) **

 

Actually, there is a built-in NAND, so this can be done without out the mynand module:

 

   // note that built-in gates have outputs as first parameters

   // with standard gates, normal to use plain parameter notation

   nand nand1(f, a, b), nand2(f1, a, b); 

 

 

Example: R-S Latch

 

_  _

Operation table

_    _

S    R    Q

0    0     unstable

0    1     1

1    0     0

1    1     hold (keep value)

 

module rsff(Q, Qbar, Sbar, Rbar);

  output Q, Qbar;

  input Sbar, Rbar;

  nand n1(Q, Sbar, Qbar);

  nand n2(Qbar, Rbar, Q);

endmodule

 

module rsff_tb;

  reg set, reset; wire q, qbar;

  rsff m1(q, qbar, ~set, ~reset);

  initial

  begin

    $monitor($time, "  set =%b, reset= %b, q=%b", set, reset, q);

  set =0; reset = 0;

  #5 reset = 1;

  #5 reset = 0;

  #5 set = 1;

  #5 set = 0;

  #20 $finish;

  end

endmodule

 

sf06.cs.umb.edu$ vvp a.out

                   0  set =0, reset= 0, q=x   <--reports unknown signal (hold of garbage)

                   5  set =0, reset= 1, q=0

                  10  set =0, reset= 0, q=0

                  15  set =1, reset= 0, q=1

                  20  set =0, reset= 0, q=1

 

Docs:

Icarus Verilog: has Getting Started, other docs

Two tutorials, Strozek (Harvard) and Wawrzynek (Berkeley)

Strozek is good for explaining syntax, talks to software people

Wawrzynek is better for full examples (more of a hardware slant) and goes further

Also, text has coverage in C.4., but not good as a tutorial

Note: this is like C: no GUI, just sources, commands