CS641 Combinational and Sequential Circuits: Netlists

sf06.cs.umb.edu$ more mynand.v

// nand gate

module mynand(in0, in1, out);

input in0, in1;

output out;

assign out = ~(in0 & in1);

endmodule

sf06.cs.umb.edu$ iverilog -S -t fpga mynand.v -o mynand.netlist

sf06.cs.umb.edu$ more mynand.netlist

(edif mynand

(edifVersion 2 0 0)

(edifLevel 0)

(keywordMap (keywordLevel 0))

(status

(written

(timeStamp 0 0 0 0 0 0)

(author "unknown")

(program "Icarus Verilog/fpga.tgt")))

(external LPM_LIBRARY (edifLevel 0) (technology (numberDefinition))

(cell INV (cellType GENERIC)

(view net

(viewType NETLIST)

(interface

(port Result (direction OUTPUT))

(port Data (direction INPUT))

(property LPM_Size (integer 1))

(property LPM_Width (integer 1))

(property LPM_TYPE (string "LPM_INV"))))) <---inverter

(cell and2 (cellType GENERIC)

(view net

(viewType NETLIST)

(interface

(port Result0 (direction OUTPUT))

(port Data0x0 (direction INPUT))

(port Data1x0 (direction INPUT))

(property LPM_Size (integer 2))

(property LPM_Width (integer 1))

(property LPM_TYPE (string "LPM_AND"))))) <---AND gate

)

(library DESIGN

(edifLevel 0)

(technology (numberDefinition))

(cell mynand

(cellType GENERIC)

(view net

(viewType NETLIST)

(interface

(port in0 (direction INPUT))

(port in1 (direction INPUT))

(port out (direction OUTPUT))

)

(contents

(instance U2 (viewRef net (cellRef INV (libraryRef LPM_LIBRARY))))

(instance U1 (viewRef net (cellRef and2 (libraryRef LPM_LIBRARY))))

(net N0 (joined (portRef Data (instanceRef U2)) (portRef Result0 (instanceRef U1))))

(net N1 (joined (portRef Result (instanceRef U2)) (portRef out)))

(net N2 (joined (portRef Data1x0 (instanceRef U1)) (portRef in1)))

(net N3 (joined (portRef Data0x0 (instanceRef U1)) (portRef in0)))

)

)

)

)

(design mynand

(cellRef mynand (libraryRef DESIGN))

)

)

sf06.cs.umb.edu$ more dff.v

module dff(clock, D, Q, Qbar);

input clock, D;

output reg Q;

output Qbar;

assign Qbar = ~ Q;

always @(posedge clock)

Q = D;

endmodule // dff

sf06.cs.umb.edu$ iverilog -S -t fpga dff.v -o dff.netlist

sf06.cs.umb.edu$ more dff.netlist

(edif dff

(edifVersion 2 0 0)

(edifLevel 0)

(keywordMap (keywordLevel 0))

(status

(written

(timeStamp 0 0 0 0 0 0)

(author "unknown")

(program "Icarus Verilog/fpga.tgt")))

(external LPM_LIBRARY (edifLevel 0) (technology (numberDefinition))

(cell fd1 (cellType GENERIC)

(view net

(viewType NETLIST)

(interface

(port Q0 (direction OUTPUT))

(port Data0 (direction INPUT))

(port Clock (direction INPUT))

(property LPM_Width (integer 1))

(property LPM_Type (string "LPM_FF"))))) <--flipflop

(cell INV (cellType GENERIC)

(view net

(viewType NETLIST)

(interface

(port Result (direction OUTPUT))

(port Data (direction INPUT))

(property LPM_Size (integer 1))

(property LPM_Width (integer 1))

(property LPM_TYPE (string "LPM_INV"))))) <--inverter

)

(library DESIGN

(edifLevel 0)

(technology (numberDefinition))

(cell dff

(cellType GENERIC)

(view net

(viewType NETLIST)

(interface

(port D (direction INPUT))

(port Q (direction OUTPUT))

(port Qbar (direction OUTPUT))

(port clock (direction INPUT))

)

(contents

(instance U2 (viewRef net (cellRef fd1 (libraryRef LPM_LIBRARY))))

(instance U1 (viewRef net (cellRef INV (libraryRef LPM_LIBRARY))))

(net N0 (joined (portRef Clock (instanceRef U2)) (portRef clock)))

(net N1 (joined (portRef Result (instanceRef U1)) (portRef Qbar)))

(net N2 (joined (portRef Q0 (instanceRef U2)) (portRef Data (instanceRef U1)) (portRef

Q)))

(net N3 (joined (portRef Data0 (instanceRef U2)) (portRef D)))

)

)

)

)

(design dff

(cellRef dff (libraryRef DESIGN))

)

)