CS641 hw5 Combinational Logic Circuits, R-S Flipflop

Find the problems at the end of Appendix C, on the CD-ROM
1. C.2
2. C.6
3. C.7 
4. C.8 
5. C.13  First do the 2-bit cases using a truth table (say),
and simplify the resulting logical expressions.  For X<Y, one
way to go is
X<Y iff (X==0)*(Y>=1) + (X==1)*(Y>=2) + (X==2)*(Y>=3)
After doing the 2-bit case, use it to do the 3-bit case,
as least for the first part, X < Y.

6. C.14

7. Using Gates to hold a bit, with the R-S flip-flop (FF)
or latch.  Note the Wikipedia article on Flip-flop (electronics): 
in particular the SR NOR latch.

Go to http://logic.ly/demo/ and choose the D latch demo.
Remove the clock input and the two gates it's connected
to, and wire the switch directly to the lower nor gate
and also add another switch to the upper nor gate.
Now you have the simplest flip-flop.  See how the switches
control the lights.  The upper input is usually called
S and the lower one R.  This is called an R-S flip-flop.

a. Can you get both lights off? both lights on? top light 
on only? bottom light only?  
b. Analyze the circuit for three cases: inputs both high, 
one high either way.  These are the easy cases, and should
come out simply, i.e, the outputs are determined by the inputs.
c. Analyze the circuit for inputs both low R=S=0, and show
how there are two solutions that work.  Use variable
x for the second input of the upper NOR in your analysis.
Setting both inputs low is the "hold" action of the flip-flop.  
Which *state* the FF is in depends on how it got there.
There are two states, which we can discriminate based
on the output of the upper NOR, usually called Q.
So with both inputs 0 (R=S=0), we say there are two states,
Q=0, and Q=1.
d. Thus concentrating on Q, the output of the upper NOR,
we can see so far that from part b., that there
is a way to set Q=0 and to set Q=1.  List the input 
combos (using R and S) for these two important actions,
set Q=0 and set Q=1.

8. The bit: setting it. The two hold states of the 
R-S flip-flop mean that we can say that one bit is being 
held in it, with value shown by the Q output.
a. Explain how to get to each of the two hold states you
found in c, no matter what state the FF is now in, by
just manipulating the R and S inputs. Compare your results
with the table (which is not a truth table) in the Wikipedia 
article. Note that we never need to use R=S=1 to do the 
important things, and this input combination is avoided, 
for reasons explained in the article.

b. Setting the bit by a digital signal (D).  Design a circuit 
that takes D (data) and E (enable) inputs so that if E=1,
then Q=D by set-Q actions, but if E=0, Q is just held from
before in the FF.  Compare your circuit to the logic.ly D latch
demo (before you change it).  What is D there? E?
You may want to replace the clock there with a slower one
to see what's happening, or replace it with a switch.