CS641 hw6 Sequential Circuits
Due Wed., Apr. 20

1a. Consider two D flipflops connected in series with an 
inverter between them:  in--D-DFF-Q---inverter---D-DFF-Q-out
Again there are 4 states, just like the initial two-FF example
in class. Find the transitions, and draw the FSM, with the input/output
markings on the arrows.

1b. Use a modification of your circuit in 1a. to design a circuit
to run a pair of lights, so only one is lit at a time, shifting 
back and forth, one transition on each clock edge. You need
to wrap the output around to the input. You could try it out 
on logic.ly (optional).

2a. C-37. Note that this system, like the system of 1b., has 
no inputs, so the transitions have notation "/output", and there 
is only one transition coming out of each state (2^0 = 1).

2b. C-38.

3. C-39

4a. C-41, but you can simplify the system to have 30-second yellow
light before any 30-second red light, rather than trying making
the yellow lights last a different length of time.
b. C-42
c. C-43

5. C-36.


6. Install Verilog on your development system, and run the first
example from the Apr. 13 Verilog Intro handout, mynand.v and 
mynand_tb.v.  Try breaking it by changing "reg a" to "wire a",
and also separately changing "wire f" to "reg f". Report on
the errors, and any problems you had with installation.