CS641 hw7 Verilog Programming

1. C.18. For each, name the circuit block and/or explain what it does.

2. C.19 The D latch is shown in Fig. C.8.2. Write a testbed that
follows Fig. C.8.3 and prints out D, C, Q, and the expected Q
after each transition (i.e., use $monitor).

3. C.20 for decoder only. Use individual bits A, B, O0, O1, O2, O3
first, for "decoder" in decoder1.v, and then 2 multibits addr and 
out, for "decoder" decoder2.v. For the latter, you can use 1 << addr, 
just like C.

Write a testbed decoder_tb.v that takes a decoder (either one) 
and puts it through its paces.  If you want, you can use repeat as in
testmux2 of W's (i.e. Berkeley's) tutorial, but with only 4
cases, it's not really necessary.

4. Consider the traffic light code on pg. C-72. See 
$cs641/hw7/traffic_lite.v for the book's code.  There is
a bug in this code.

Write a testbed for the traffic light, that has in part, to start off:
#0 clock=1; expectedNS = 1;  // lite starts off NS
#5 clock=0; NSCar=1;        // change car-status while clock=0
#5 clock=1; expectedNS = 1;  // clock edge--> take changed input, do output-->report
#5 clock=0; NSCar=1; EWCar=1;
...
$monitor("EWCar = %d, NSCar=%d, EWLite=%d, NSLite=%d, expectedNS=%d, time = %d",
 EWCar, NSCar, EWLite, NSLite, expectedNS, $time);
Note that the monitor does not report changes in the inputs done
when the module is not actually accepting input. It's smart
about reporting the important changes in signals.

So far, the bug won't show. Keep going, through more expected
transitions, and show the bad behavior.  Then fix it and rerun.
Show your before and after runs, and testbed code.

5. Implement the "electronic eye" of C.37 and C.38 in Verilog, in
electronic_eye.v, and testbed electronic_eye_tb.v.  In particular,
have the testbed print out the table 
WRONG: on pg. C-69 
FIXED: as in the hw6 solutions and shown below
by using the component under test to generate the "next state" values
ADDED: and the output values.

        Outputs
PS  NS  M  R  L 
0   1   1  0  0
1   2   0  1  0
2   3   1  0  0
3   0   0  0  1

6. Write a testbed for the register file, pg. 57 and in ./hw7,
that fills the 
WRONG:first 100 locations with 0, 1, 2, ..., 99, and then 
WRONG:goes back and reads every 10th value (#0, #10, ... #90) 
FIXED: 32 registers with 0, 1, ..., 31 and then
FIXED: goes back and reads them all 
and compares 
them with the expected contents, and prints out the value read and 
the expected value, and !!ERROR!! if they don't agree.

Here we need to use the looping capability of Verilog
shown in testmux2 of W's tutorial. 

Added note re Alex's message:
Change the register numbers from [5:0] to [4:0], 5 bits each.