CS641 hw8
due Wed., May 11, last class
Pipelining and Instruction Set Design

P&H problems
1. 4.1.1ab, 4.1.2ab One-cycle CPU basics
2. 4.12.1-3 basic pipelining
3. 4.13.1a show pipeline execution diagram, see pg. 365 for "type"
   4.13.2a, 4.13.3a, 4.13.5a   Data dependencies
4. 4.14.3a Show pipeline execution diagrams  Branch stalls
5. 4.22.1a, 4.22.2a  Delay slots

6. For the tiny computer, change add to addi, to trim off the "extra" clock cycle
in the add case.  This is ultra6.v.  It has an instruction set as follows:
LOAD addr    (load contents of memory addr into AC)
STORE addr   (store contents of AC into memory addr)
ADDI amt     (add amt to AC)
JUMP addr    
Note that to the programmer, there is only one register, AC, plus memory.

7. Now that we have the same number of clock cycles for each instruction, 
consider pipelining this CPU.  What needs to be in the pipeline registers?
Give an example of a data hazard.  What should happen when the jump occurs?
Optionally, implement it.

8. Optional. This computer can't add up an array of numbers, or generate an array,
because the memory address is fixed in the instructions.   Let's fix this.
Make the MA be a programmer-visible register
for memory addresses, like this:

LA  addr    (load addr into MA)
LOAD        (load contents of memory using addr from MA, and load contents into AC)  
STORE       (store contents of AC into meory at addr in MA)
ADDI amt    (add amt to AC)
ADDIAM amt  (add amt to MA)
JUMP addr
HALT addr    (stop when MA reaches addr, nop otherwise)

Implement this tiny computer, and deliver it with two programs:
ultra7.v    does original program, generating sequence of numbers in AC
ultra8.v    has array of (10, 20, 30) in memory to start. Adds it up
            and leaves the sum in AC