CS641 Class 27

Final Review, Teacher Evaluations

Final Exam: Mon, 5/16, 6:30 (6:05) M-1-612: just on material since midterm (more exactly, since we started on Circuit theory, somewhat before the midterm)

Looking at syllabus: we covered all CS61c topics except virtual memory. This is covered in cs644, perhaps offered next spring.

Since midterm: logic circuits, CPU components, CPU datapath and control, pipelining

What materials?

All of the two handouts linked from the Syllabus:

1.       CS61c: Representations of Combinational Logic Circuits

2.       CS61c: State Elements: Circuits That Remember

and all of another 61c handout:

3.       CS61c: Verilog Tutorial

Appendix C: we used parts

C.1, C.2 Intro, Gates, etc.: overlaps CS61c #1

C.3 Decoders, MUXs: CS61c #1 is enough, also, we didn’t cover PLAs

pg. C-17-C-18 Don’t Cares: covered here, not elsewhere

C.4 HDLs: Verilog vs. VHDL, datatypes, structure of programs: read now, not good tutorial, but useful after basics.

C.5 ALUs useful, covered slightly simpler ALU in class

C.6 Faster addition: skip

We realize that the circuit we came up with is too slow, and that addition in “just combinational”, so can believe there are better ways.

C.7 Clocks: good to read, some confusion on clocks seems to remain

C.8 Memory Elements: FFs and latches. Note that the graphed example here is a falling-edge FF, but the code is for a rising edge. Register files, including Verilog: this is our coverage. Note the combinational behavior of reading a register, vs. clocked behavior of writing, important to understandeing the single-cycle CPU

C.9 on SRAMs and DRAMs: can skip. We’re using the register file as our simple model of memory based on registers, which is what SRAM (static RAM) is.  DRAM is made out of capacitors, plus digital circuitry—that’s all we covered.

C.10 FSMs. Important coverage. Don’t worry about Mealy vs. Moore machines: we just used Moore machines, as stated on pg. C-68. Note that a FSM circuit always has a clock to tell it when to change state.  To turn Fig. C.10.1, pg. C-68 into a Moore machine, cross out the connection from input to output function.  The clock is saying when to sample the current state to drive the two combinational circuits in ovals.

C.11 Timing Methodologies. We only covered edge-triggered timing for sequential circuits. We assume that that clock edge arrives at all components at the same time to close enough approximation.  The old results (sampled from registers at the last clock edge) are still available for inputs for this cycle. We did some closer timing examples, but I won’t ask for this on the final. So skip this section.

C.12 Field Programmable Devices: only mentioned, skip.

 

Sequential vs. Combinational Circuits

A circuit made of gates with no feedback is combinational: TT, inputs--> outputs

Examples: MUX, Decoder, adder, ALU, important parts of control circuitry

The D latch is a circuit made only of gates, with feedback, our only example of this case.  It’s a stepping stone from combinational to sequential circuits. We never used it in larger circuits. Instead, used D FF.

D FF: made of gates but mysteriously so, so we don’t count it as a “gate”, but instead as an elemental unit of a sequential circuit. It has clock, D, reset inputs, Q and notQ outputs.  All our registers are made from D FFs.

We used only edge-triggered sequential circuits, so they all need a clock and change state at the clock edge.

Examples: register, counter, accumulator, CPU, FSMs: all based on D FFs, plus possibly some combinational circuitry.

Edge-triggered sequential circuit:

One clock signal goes to all D FFs, at the same time

Outputs follow in a few moments, then get held to just past the next clock edge

They possibly pass through some combinational circuitry, delaying the signal a bit more

After a small interval, the signals are stable on the other side of the combinational circuitry, until the corresponding time after the next clock edge

So the next clock edge samples the results of this cycle as stable signals on the inputs of whatever is “next” in the circuit.

The only hybrid combinational/sequential device we studied was the register file. It counts as “sequential”, since not purely combinational.

It is combinational on read, sequential on write

This was important in understanding the single-cycle CPU.

Sequential vs. Combinational Verilog Code

assign  is for combinational code only. No Begin-end is used with it, though you can list assignments

assign Sum=A^B, Carry=A&B;

lhs needs to be wire(s) to carry out the computed live signal

Example on C-23 for half_addr

We can use always for combinational code too: Now need reg’s, since lhs of assignments in always need reg’s.

output reg Sum, Carry;

always @(A, B)    <--at changes in A and B, recalc.

begin

  Sum = A^B;  //”assignment”  but not an “assign”

  Carry= A&B;

end

 

or use <= here, but above does not cause FFs in netlist, so Verilog has not used real registers for this.

always @(posedge clock)   is only used in sequential code

Ex: D FF, reg4, register file, FSM

But we can have sequential code without this: tiny computer, uses reg’s plus time intervals.

acc on pg. 14 of V. tutorial: instantiates sequential components, so @(posedge clock) happens inside them.

Always and initial are similar: containers for procedural/behavioral code, can’t be nested.

Procedural/behavioral code: C-like constructs begin/end, if/then/else, case, loops

Always loops back, initial only runs once

We have never seen initial inside a module instantiated by another module, i.e., we’ve only seen it running a testbed.

But it can be: could add it to registerfile to clear memory at power-up.