ISMVL 2002

FINAL PROGRAM

LA Lipke Auditorium, Science Building, 2nd floor

SA Small Science Auditorium, Science Building, 1st floor

FC Faculty Club, Library Building, 11th floor

 

THURSDAY, May 16

 

9:30: SYMPOSIUM OPENING, (LA)

 

Chancellor Jo Ann Gora

Dan Simovici, Chair of ISMVL 2002

 

 

10:00-11:00: GENERAL SESSION, (LA)

(chair: D. Simovici)

 

Sergiu Rudeanu: Equations in the Algebra of Logic

 

Coffee break 11:00 11:15

 

11:15 12:45 ALGEBRA I (LA)

(chair M. Mukaidono)

 

H. Machida, I. G. Rosenberg and M. Miyakawa: Some Results on

Centralizers of Monoids in Clone Theory

 

B.A. Romov: Partial Hyperclones on a Finite Set

 

Michiro Kondo: On structures of weak interlaced bilattices

 

12:45 2:00 Lunch and Executive Committee Meeting (FC)

 

2:00 4:00 LOGICAL DESIGN I (LA)

(chair M. Perkowski)

 

Claudio Moraga: Improving the characterization of p-valued threshold

functions

 

E. Dubrova: A conjunctive decomposition of multiple-valued functions

 

D. Popel, A. Dani, Sierpinski: Gaskets for Logic Functions

Representation

 

Noboru Takagi and Kyoichi Nakashima: Logic for Static Hazard

Detection of Multiple-Valued Logic Circuits with Tsum, Min, and

Literals

 

Coffee Break 4:00 4:30

 

Parallel Sessions:

 

4:30 6:30 CIRCUITS I (LA)

(chair M. Kameyama)

 

Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, and Tatsuo

Higuchi: Multiple-Valued Data Recovery Techniques for Band-Limited

Channels in VLSI

 

Takao Waho, Shin-ya Kobayashi, and Koji Matsuura: An Impact of

Introducing Multi-Level Signals to a Bandpass Cascaded Delta-Sigma

Modulator

 

Y.B.Guo, K.W. Current, Voltage Comparator Circuits for

Multiple-Valued CMOS Logic

 

4:30 6:30 LOGICAL DESIGN II (SA)

(chair M. Miller)

 

D.Jankovic, R.S.Stankovic, R. Drechsler Efficient Calculation of

Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic

Functions

 

K. J. Adams, J. McGregor: A Calculation Laboratory for Quaternary

Reed-Muller Canonical Forms and Some New Statistical Results

 

B.Polianskikh, Z. Zilic: Design and Implementation of Error Detection

and Correction Circuitry for Multilevel Memory Protection

 

M. Natsui, T. Aoki, T. Higuchi: Parallel Evolutionary Graph Synthesis

on a PC Cluster and Its Application to Multi-Valued Circuit Synthesis

 

 

FRIDAY, May 17

 

9:00 10:00 GENERAL SESSION (LA)

(chair: Sergiu Rudeanu)

Consequence and Complexity in Infinite-Valued Logic: A Survey (D. Mundici)

 

10:00 10:30 Coffee Break

 

Parallel Sessions

 

10:30 12:30 SPECTRAL TECHNIQUES (LA)

(chair Z. Zilic)

 

R.S. Stankovic, J. Astola: Some remarks on linear transform of

variables in representation of Adders by word-level expressions and

spectral transforms decision diagrams.

 

M.A. Thornton, D.M. Miller, W.J. Townsend: Chrestenson Spectrum

Computation Using Cayley Color Graphs

 

Z.Zilic, K. Radecka, The Role of Super-Fast Orthogonal Transforms

in Speeding up Quantum Computations

 

Bogdan J. Falkowski and Beata T. Olejnicka: Multiple-Valued and

Spectral Approach to Lossless Compression of Binary, Gray Scale and

Color Biomedical Images.

 

10:30 12:30 CIRCUITS II (SA)

(chair B. Falkowski)

 

E. Zaitseva, V. Levashenko: Design of dynamic deterministic

reliability indices Contact author: Dr. E. Zaitseva

 

Naotake Kamiura, Teijiro Isokawa, and Nobuyuki Matsui: On

Multiple-Valued PODEM Based on Static Testability Measures and

Dynamic Testability Measures.

 

Xunwei Wu, Penjun Wang, and Yinshui Xia: Design of Ternary Schmitt

Triggers Based on Its Sequential Characteristics

 

Hiromitsu Kimura, Takahiro Hanyu, and Michitaka Kameyama:

Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor

Storage and Charge Addition

 

12:30 2:00 Lunch and Symposium Committee Meeting

 

2:00 3:00 GENERAL SESSION (LA)

(chair T. Sasao)

 

Optimization of Multi-Valued Multi-Level Networks (M. Gao, J. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa, and R. Brayton)

 

3:00 3:30 Coffee Break

 

Parallel Sessions

 

3:30 5:00 ALGEBRA II (LA)

(chair M. Miyakawa)

 

Hiroaki Kikuchi and Noboru Takagi: de Morgan Bisemilattice of Fuzzy

Truth Value

 

Tomoko Ninomiya, Masao Mukaidono: Independence of Each Axiom in a Set

of Axioms and Complete Sets of Axioms for Boolean Algebras

 

I.Rosenberg, D.A.Simovici, S.Jaroszewicz: On Functions Defined on

Free Boolean Algebras

 

3:30 5:00 LOGICAL DESIGN III (SA)

(chair Takahiro Hanyu)

 

S. Yanushkevich, P.Dziurzanski, V.Shmerko, The Word-Level Models for

Efficient Neural-Like Computation of Multiple-Valued Functions. PART

1: LAR Based Model

 

Tomaszewska, S. Yanushkevich, V. Shmerko, The Word-Level Models for

Efficient Neural-Like Computation of Multiple-Valued Functions. PART

2: LWL Based Model

 

Ilia Polian, Piet Engelke, Bernd Becker Efficient Bridging Fault

Simulation of Sequential Circuits Based on Multi-Valued Logics

5:00-6:00 Plenary Session (LA)

7:30-10:00 Banquet at Park Plaza Hotel

 

 

SATURDAY, May 18

 

 

 

9:00 10:00 GENERAL SESSION (LA)

(chair C. Moraga)

 

N. Takagi: Multiple-Valued-Digit Number Representation in Arithmetic Circuit Algorithms

 

10:00 10:30 Coffee Break

 

Parallel Sessions

 

10:30 12:30 DECISION DIAGRAMS (LA)

(chair R. Brayton)

 

Masahiro Miyakawa, N. Otsu, I.G. Rosenberg: Variable Selection Heuristics and Optimum Decision

Trees - An Experimental Study

 

D. M. Miller, R. Drechsler: On the Construction of Multiple-Valued

Decision Diagrams

 

R. Drechsler:

Evaluation of Static Variable Ordering Heuristics for MDD Construction

 

Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi and Munehiro Matsuura:

Representations of Logic Functions using QRMDDs

 

10:30 12:00 CIRCUITS III (SA)

(chair N. Takagi)

 

Tsukasa Ike, Takahiro Hanyu, and Michitaka Kameyama: Fully

Source-Coupled Logic Based Multiple-Valued VLSI

 

Sung Il Han, Seung Yong Park, Hyeon Kyeong Seong, and Heung Soo Kim:

A Current-Mode Folding/Interpolating CMOS Analog to Quaternary

Converter Using Binary to Quaternary Encoding Block

 

Motoi Inaba, Koichi Tanno, and Okihiko Ishizuka: Multi-Valued

Flip-Flop with Neuron-CMOS NMIN Circuits